Ritera is building AI systems for chip design, aimed at closing the loop between models and the silicon that runs them. Better chips enable stronger models; stronger models design better chips.

The project treats semiconductor design as a learning problem: agents that place, route, and optimize circuits against power, performance, and area, then improve from every layout they produce.

The long-term goal is recursive intelligence in hardware — systems that compress design cycles from years toward days, and that co-evolve with the workloads they are meant to accelerate.

Approach

AI for chip design. Ritera applies reinforcement learning, graph neural networks, and specialized search to physical design: floorplanning, placement, routing, and timing closure under real foundry constraints.

Chip design for AI. The same stack targets silicon built for modern model workloads — dense attention, sparse activation, low-precision arithmetic, and memory-bound inference — so each generation of hardware feeds the next generation of design agents.

Closed loop. Layout quality becomes training signal. Successful designs transfer across blocks and process nodes. Failures become curriculum. The loop is the product.

Technology

Selected pillars of the Ritera stack.

• Placement agents Deep RL policies that place macros and standard cells against congestion, wirelength, power, and timing
• Circuit graph models Edge-aware graph networks that encode netlists and generalize across blocks and chip families
• Timing and PPA feedback Fast surrogate models and EDA-in-the-loop rewards for power, performance, and area
• Workload-aware silicon Design targets shaped by AI training and inference profiles, not static generic SoC templates
• Recursive improvement Each tapeout and each simulated layout strengthens the next design policy

Focus

Physical design automation. Compressing placement and routing cycles while meeting production-grade constraints.

Accelerator architecture. Exploring datapaths, memory hierarchy, and interconnect for recursive model–silicon co-design.

Self-improving toolchains. Turning chip design itself into a continually learning system rather than a one-off expert workflow.

Research to silicon. Bridging academic methods and foundry reality — measurable PPA, manufacturable layouts, and repeatable gains across generations.

Team

The people building Ritera come from Harvard, Micron Technology, and NXP Semiconductors — research and industry experience across AI, memory, and semiconductor design.

Contact

For partnerships, research collaboration, or conversations about AI chip design and recursive intelligence, get in touch.